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19-1413; Rev 0; 12/98
KIT ATION EVALU E AILABL AV
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
General Description Features
o Monolithic 16-Bit, 1Msps A/D Converter o Single +5V Supply o VREF Differential Input Voltage Range o 87dB SNR for fIN = 100kHz o 91dB SFDR for fIN = 100kHz o 273mW Low-Power Dissipation o 0.5LSB Differential Nonlinearity Error o Three-State, Two's Complement Output Data o On-Demand Self-Calibration o Pin-Compatible 14-Bit Versions Available (1Msps MAX1205, 2.2Msps MAX1201)
MAX1200
The MAX1200 16-bit, monolithic, analog-to-digital converter (ADC) is capable of conversion rates up to 1Msps. This CMOS integrated circuit uses a fully differential, pipelined architecture with digital error correction and a short self-calibration to ensure 16-bit linearity at full sample rates. An on-chip track/hold (T/H) maintains superb dynamic performance up to the Nyquist frequency. The MAX1200 operates from a single +5V supply. The fully differential inputs allow an input swing of VREF. The reference is also differential with the positive reference (RFPF) typically connected to +4.096V and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are provided to compensate for any resistive divider action that may occur. A single-ended input is also possible using two operational amplifiers. Power dissipation is typically only 273mW at +5V, at a sampling rate of 1Msps. The device employs a CMOScompatible, 16-bit parallel, two's complement output data format. For a higher sampling speed (up to 2.2Msps) but lower resolution (14-bit), select the MAX1201, a pin-compatible version of the MAX1200. The MAX1200 is available in an MQFP package and operates over the commercial (0C to +70C) and extended-industrial (-40C to +85C) temperature ranges.
Ordering Information
PART MAX1200ACMH MAX1200BCMH MAX1200AEMH MAX1200BEMH TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 44 MQFP 44 MQFP 44 MQFP 44 MQFP DNL (LSB) 0.5 -- 0.5 --
Pin Configuration
TOP VIEW
TEST0
34
INP RFNS RFNF
40 39 38
High-Resolution Imaging Communications Scanners Data Acquisition Instrumentation
ST_CAL AGND AVDD AGND AGND AVDD DOR D15 D14 D13 D12
1 2 3 4 5 6 7 8 9 10 11
44
43
42
41
37
36
35
RFPS RFPF CM
INN N.C. N.C.
Applications
END_CAL
33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
MAX1200
OE DAV CLK DVDD DGND DGND DVDD TEST1 D0 D1 D2
D11 D10
D9 D8 DRVDD
DGND D7
D6 D5 D4
MQFP ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
D3
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND, DGND ..........................................................+7V DVDD to DGND, AGND..........................................................+7V DRVDD to DGND, AGND .......................................................+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM..........(AGND - 0.3V) to (AVDD + 0.3V) Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 44-Pin MQFP (derate 11.11mW/C above +70C).......889mW Operating Temperature Ranges (TA) MAX1200_CMH ..................................................0C to +70C MAX1200_EMH................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz; digital output load 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER ANALOG INPUT Input Voltage Range (Note 2) Input Resistance (Note 3) Input Capacitance EXTERNAL REFERENCE Reference Voltage (Note 4) Reference Input Resistance TRANSFER CHARACTERISTICS Resolution (No missing codes; Note 5) Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise DYNAMIC SPECIFICATIONS (Note 6) Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Aperture Jitter Full-Power Bandwidth Small-Signal Bandwidth 2 tACQ tOVR tAD tAJ To full-scale step (0.006%) fSAMPLE fSAMPLE = fCLK / 2 1.024 4 125 450 3 5 3.3 78 Msps fSAMPLE Cycles ns ns ns psRMS MHz MHz RES INL DNL MAX1200A MAX1200B -0.2 -5 -1 After calibration, guaranteed for MAX1200A only 16 3.5 0.5 0.6 0.003 -3 75 +0.2 5 +1 Bits LSB LSB %FSR %FSR VRMS VREF RREF 700 4.096 1000 4.5 V VIN RI CI Per side in track mode Single-ended Differential 4.096 4.096 55 21 V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz; digital output load 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS VRFPS = 4.096V, VRFNS = AGND Signal-to-Noise Ratio (Note 5) SNR VRFPS = 3.5V, VRFNS = 1.5V fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz 4.75 3 0.4 3 10pF loads on D0-D15 and DAV 0.1 273 0.1 PSRR Offset Gain 55 55 77 80 85 84 78 MIN 83 TYP 87 84 83 83 81 80 91 89 88 92 91 90 -87 -86 -85 -90 -89 -88 84 82 81 82 80.5 79.5 5 51 5.25 70 5.25 1.2 DVDD 0.6 377 V mA V mA V mA mW sec dB dB -84 dB -82 dB dB MAX UNITS
MAX1200
VRFPS = 4.096V, VRFNS = AGND Spurious-Free Dynamic Range (Note 5) SFDR VRFPS = 3.5V, VRFNS = 1.5V
VRFPS = 4.096V, VRFNS = AGND Total Harmonic Distortion (Note 5) THD VRFPS = 3.5V, VRFNS = 1.5V
VRFPS = 4.096V, VRFNS = AGND Signal-to-Noise Ratio plus Distortion (Note 5) SINAD VRFPS = 3.5V, VRFNS = 1.5V POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS
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3
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
TIMING CHARACTERISTICS (Figures 7, 8, 9)
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Conversion Time Clock Period Clock HIGH Time Clock LOW Time Acquisition Time Output Delay DAV Pulse Width CLK-to-DAV Rising Edge Data Access Time Bus Relinquish Time Calibration Time SYMBOL tCONV tCLK tCH tCL tACQ tOD tDAV tS tAC tREL tCAL ST_CAL = DVDD CL = 20pF 187 187 CONDITIONS MIN TYP 4 / fSAMPLE 488 244 244 tCLK / 2 70 1 / fCLK 65 16 16 17,400 145 75 75 150 301 301 MAX UNITS ns ns ns ns ns ns ns ns ns ns fCLK Cycles
DIGITAL INPUT AND OUTPUT CHARACTERISTICS
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input LOW Voltage Input HIGH Voltage Input Capacitance CLK Input LOW Voltage CLK Input HIGH Voltage CLK Input Current CLK Input Capacitance Digital Input Current Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance VCLK VCLK ICLK CCLK IIN VOL VOH ILEAKAGE COUT VIN = 0 or DVDD ISINK = 1.6mA ISOURCE = 200A DVDD - 0.4 VIN = 0 or VDD AVDD - 0.8 1 9 0.1 70 DVDD - 0.03 0.1 3.5 10 10 400 10 SYMBOL VIL VIH DVDD - 0.8 4 0.8 CONDITIONS MIN TYP MAX 0.8 UNITS V V pF V V A pF A mV V A pF
Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation. Note 2: For unipolar mode, the analog input voltage, VINP, must be within 0 and VREF, VINN = VCM / 2; where VREF = VRFPS - VRFNS. For differential mode, the analog input voltages VINP and VINN must be within 0 and VREF; where VREF = VRFPS - VRFNS. The common-mode voltage of the inputs INP and INN is VCM = (VRFPS + VRFNS) / 2. Note 3: RI varies inversely with sample rate. Note 4: Minimum and maximum parameters are not tested. Guaranteed by design. Note 5: Calibration remains valid for temperature changes within 20C and power-supply variations 5%. Guaranteed by design. Note 6: All AC specifications are shown for the differential mode.
4
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
__________________________________________Typical Operating Characteristics
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND; VCM = +2.048V, differential input, fCLK = 2.048MHz, calibrated, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc01
MAX1200
DIFFERENTIAL NONLINEARITY vs. TWO'S COMPLEMENT OUTPUT CODE
MAX1200toc02
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz)
(dBFS) 110 100 90 SFDR (dB) 80 70 (dBc) 60 50 40 30
MAX1200toc03
5 4 3 2
1.0 0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75
120
INL (LSB)
1 0 -1 -2 -3 -4 -5 -32768 -16384 0 16384 32768
-1.0 -32,768
-16,384
0
16,384
32,768
-80
-70
-60
-50
-40
-30
-20
-10
0
TWO'S COMPLEMENT OUTPUT CODE
TWO'S COMPLEMENT OUTPUT CODE
INPUT AMPLITUDE (dBFS)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY
MAX1200 toc04
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
-76 AIN = -20dBFS -78 THD (dB) SNR (dB) -80 -82 -84 -86 AIN = -6dBFS
MAX1200 toc05
SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY
AIN = -0.5dBFS 85 AIN = -6dBFS
vsMAX1200 toc06
86 84 82 80 SINAD (dB) 78 76 74 72 70 68 1 10 100 AIN = -20dBFS AIN = -6dBFS AIN = -0.5dBFS
-74
90
80
75
70 AIN = -0.5dBFS 65 1 10 100 1000 1 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) AIN = -20dBFS
-88 -90 1000
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz)
MAX1200 toc07
TYPICAL FFT, fIN = 99.5kHz, 8192 VALUE RECORD
MAX1200 toc08
TYPICAL FFT, fIN = 504.5MHz, 8192 VALUE RECORD
-15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150
MAX1200 toc09
85
0 -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135
0
84 SINAD (dB)
83
82
81
80 0.1 1 SAMPLE RATE (Msps) 10
-150 0 200 400 600 FREQUENCY (kHz)
0
200
400
600
FREQUENCY (kHz)
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5
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
Typical Operating Characteristics
(AVDD = +5V 5%, DVDD = DRVDD = +3.3V, VRFPS = +3.5V, VRFNS = +1.5V; VCM = +2.5V, differential input, fCLK = 2.048MHz, calibrated, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc11
DIFFERENTIAL NONLINEARITY vs. TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc12
2.0 1.5 1.0
0.8 0.6 0.4 DNL (LSB)
100 90 80 SFDR (dB) 70 60 50 40 30 20 10 0
(dBFS)
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -32,768 -16,384 0 16,384 32,768
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -32,768 -16,384 0 16,384 32,768
(dB)
-90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT AMPLITUDE (dBFS)
0
TWO'S COMPLEMENT OUTPUT CODE
TWO'S COMPLEMENT OUTPUT CODE
SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY
MAX1200 toc14
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
MAX1200 TOC15
SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY
MAX1200 toc16
84 82 80 78 SINAD (dB) 76 74 72 70 68 66 64 62 1 AIN = -20dBFS 10 100 AIN = -0.5dBFS
-77 -79 -81 AIN = -20dBFS
85 AIN = -0.5dBFS
80
AIN = -6dBFS THD (dB)
-83 -85 -87 -89 AIN = -6dBFS SNR (dB)
75
AIN = -6dBFS
70
65 -91 -93 1000 1 10 100 1000 INPUT FREQUENCY (kHz) AIN = -0.5dBFS 60 1 AIN = -20dBFS 10 100 1000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz)
MAX1200 toc17
TYPICAL FFT, fIN = 99.5kHz, 8192 VALUE RECORD
MAX1200 toc18
TYPICAL FFT, fIN = 504.5MHz, 8192 VALUE RECORD
-15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150
MAX1200 toc19
84 83 82 SINAD (dB) 81 80 79 78 0.1 1 SAMPLE RATE (Msps)
0 -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150
0
10
0
200
400
600
0
200
400
600
FREQUENCY (kHz)
FREQUENCY (kHz)
6
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MAX1200 toc13
2.5
1.0
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz)
110
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
Pin Description
PIN 1 2, 4, 5 3, 6 7 8 9 10 11 12 13 14 15 16 17, 28, 29 18 19 20 21 22 23 24 25 26 27, 30 31 32 33 34 35 36 37 38 39 40 41, 42 43 44 NAME ST_CAL AGND AVDD DOR D15 D14 D13 D12 D11 D10 D9 D8 DRVDD DGND D7 D6 D5 D4 D3 D2 D1 D0 TEST1 DVDD CLK DAV OE TEST0 CM RFPF RFPS RFNF RFNS INP N.C. INN END_CAL Digital Input to Start Calibration. ST_CAL = 0: Normal conversion mode. ST_CAL = 1: Start self-calibration. Analog Ground Analog Power Supply, +5V 5% Data Out-of-Range Bit Bit 15 (MSB) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Digital Power Supply for the Output Drivers. +3V to +5.25V, DRVDD DVDD Digital Ground Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Test Pin 1. Do not connect. Digital Power Supply, +3V to +5.25V Input Clock. Receives power from AVDD to reduce jitter. Data Valid Clock. This clock can be used to transfer the data to a memory or any other data acquisition system. Output Enable. OE = 0: D0-D15 and DOR are high impedance. OE = 1: All bits are active. Test Pin 0. Do not connect. Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages. Positive Reference Voltage, Force Input Positive Reference Voltage, Sense Input Negative Reference Voltage, Force Input Negative Reference Voltage, Sense Input Positive Input Voltage Not Connected. No internal connection. Negative Input Voltage Digital Output for End of Calibration. END_CAL = 0: Calibration in progress. END_CAL = 1: Normal conversion mode. 7 FUNCTION
MAX1200
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
Detailed Description
Converter Operation
The MAX1200 is a 16-bit, monolithic analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. It uses a multistage, fully differential, pipelined architecture with digital error correction and self-calibration to provide typically 91dB spurious-free dynamic range at a 1Msps sampling rate. It also provides excellent SNR and THD performance up to the Nyquist frequency. This makes the device suitable for applications such as data acquisition, high-resolution imaging, scanners, digital communication, and instrumentation. Figure 1 shows the simplified, internal structure of the ADC. A switched-capacitor, pipelined architecture is used to digitize the signal at a high throughput rate. The first four stages of the pipeline use a low-resolution quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to subtract the quantized analog signal from the input. The residue is then amplified with a fixed gain and passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm which corrects for mismatches between the capacitors in the switched-capacitor MDAC. Note that the pipeline introduces latency of four sampling periods between the input being sampled and the output appearing at D15-D0. While the device can handle both single-ended or differential inputs (see the Requirements for Reference and Analog Signal Inputs section), the latter mode of operation will guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation: * Twice as much signal input span * Common-mode noise immunity * Virtual elimination of the even-order harmonics * Less stringent requirements on the input signal processing amplifiers
Requirements for Reference and Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) are used for both the reference and analog inputs (Figure 2). This allows either single-ended or differential signals to be used in the reference and/or analog signal paths. The signal voltage on these pins (INP, INN, RFP_, RFN_) should never exceed the analog supply rail, AVDD, nor fall below ground.
RFP_
RFN_
CM
AVDD
AGND
STAGE1 INP INN S/H ADC MDAC 8X
STAGE2
STAGE3
STAGE4 ADC
CLK DVDD ST_CAL DGND OE DRVDD
CLOCK GENERATOR
DAV CORRECTION AND CALIBRATION LOGIC END_CAL
MAX1200
OUTPUT DRIVERS
DOR
D15-D0
Figure 1. Internal Functional Diagram
8 _______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
CM RFPF INP RFNF INN
RFPS RFPF
RFNF RFPF CM RFNS
Figure 2. Simplified MDAC Architecture
Figure 3. Equivalent Input at the Reference Pins. The sense pins should not draw any DC current.
Choice of Reference
It is important to choose a low-noise reference such as the MAX6341, which can provide both excellent load regulation and low temperature drift. The equivalent input circuit for the reference pins is shown in Figure 3. Note that the reference pins drive approximately 1k of resistance on-chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within one clock cycle. Carefully choose an appropriate driving circuit (Figure 4). The capacitors at the reference pins (RFPF, RFNF) provide the dynamic charge required during each clock cycle, while the op amps ensure accuracy of the reference signals. These capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors. The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF) would be driven to +4.096V, and the negative reference pin (RFNF) connected to analog ground for best SNR performance. If THD performance is more important to the application than signal-to-noise ratio, choose a lower level, differential voltage such as V RFPS = +3.5V and VRFNS = +1.5V. There are sense pins, RFPS and RFNS, which can be used with external amplifiers to compensate for any resistive drop on these lines, internal or external to the chip. Ensure a correct reference voltage by using proper Kelvin connections at the sense pins.
VRFP = +4.096V 5k CHIP BOUNDARY RFPF
MAX410
5k
RFPS
VRFN = 0
RFNF
MAX410
RFNS
CM
MAX410
Figure 4. Drive Circuit for Reference Pins and Common-Mode Pin
Common-Mode Voltage
The switched-capacitor input circuit at the analog input allows signals between AGND and the analog power supply. Since the common-mode voltage has a strong
influence on the performance of the ADC, the best results are obtained by choosing V CM = (V RFPS + VRFNS) / 2. This can be achieved by using a resistive divider between the two reference potentials. Figure 4 shows a typical driving circuit for good dynamic performance.
9
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
Analog Signal Conditioning
For single-ended inputs, the negative analog input pin (INN) is connected to the common-mode voltage pin (CM) and the positive analog input pin (INP) is connected to the input. To take full advantage of the ADC's superior AC performance up to the Nyquist frequency, drive the chip with differential signals. In communication systems the signals may inherently be available in differential mode; however medical and/or other applications may only provide single-ended inputs. In this case, convert the single-ended signals into differential ones by using the circuit recommended in Figure 5. Use low-noise, wideband amplifiers, such as the MAX4108, to maintain the signal purity over the full-power bandwidth of the MAX1200 input. Lowpass or bandpass signals may be required to improve the signal-to-noise and distortion of the incoming signal. For low-frequency signals (<100kHz), active filters may be used. For higher frequencies, passive filters are more convenient.
Single-Ended to Differential Conversion Using Transformers
An alternative single-ended to differential-ended conversion method is a balun transformer such as the CTX03-13675 from Coiltronics. An important benefit of these transformers is their ability to level-shift singleended signals referred to ground on the primary side to optimum common-mode voltages on the secondary side. At frequencies below 20kHz the transformer core begins to saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need a 50% duty cycle clock. To avoid this constraint, the MAX1200 provides a divide-by-two circuit to relax this requirement. The clock generator should be chosen commensurate with the frequency range, amplitude, and slew rate of the signal source. If the slew rate of the input signal is small, the jitter requirement on the clock is relaxed. However, if the slew rate is high, the clock jitter needs to be kept at a minimum. For a full-scale amplitude input sine wave, the maximum possible signal-to-noise ratio (SNR) due completely to clock jitter is given by: SNRMAX = 1 2 fIN JITTER
V+
IN INP
MAX4108
For example, if fIN is 500kHz and JITTER is 10ps RMS, then the SNR limit due to jitter is about 90dB. Generating such a clock source requires a low-noise comparator and a low-phase-noise signal generator. The clock circuit shown in Figure 6 is a possible solution.
CM
VV+ 0.1F 0.1F CLK_IN INN CLK
V+
MAX4108
V+
1k
5k
MAX961
VCM 0.1F 1k
Figure 5. A simple circuit generates differential signals from a single-ended input referred to analog ground. The commonmode voltage at INP and INN is the same as CM.
10
Figure 6. Clock Generation Circuit Using Low-Noise Comparator
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
Calibration Procedure
Since the MAX1200 is based on a pipelined architecture, low-resolution quantizers ("coarse ADCs") are used to approximate the input signal. MDACs of the same resolution are then used to reconstruct the input signal, which is subtracted from the input and the residue amplified by the SC gain stage. This residue is then passed on to the next stage. The accuracy of the MAX1200 is limited by the precision of the MDAC, which is strongly dependent on the matching of the capacitors used. The mismatch between the capacitors is determined and stored in an on-chip memory, which is later used during the conversion of the input signal. During the calibration procedure, the clock must be running continuously. ST_CAL (start of calibration) is initiated by a positive pulse with a minimum width of four clock cycles, but not longer than about 17,400 clock cycles (Figure 8). The ST_CAL input may be asynchronous with the clock, since it is retimed internally. With ST_CAL activated, END_CAL goes low one or two clock cycles later and remains low until the calibration is complete. During this period, the reference voltages must be stable to less than 0.01%; otherwise the calibration will be invalid. During calibration, the analog inputs INP and INN are not used; however, better performance is achieved if these inputs are static. Once END_CAL goes high (indicating that the calibration procedure is complete), the ADC is ready for conversion. Once calibrated, the MAX1200 is insensitive to small changes (5%) in power-supply voltage or temperature. Following calibration, if the temperature changes more than 20C, the device should be recalibrated to maintain optimum performance.
MAX1200
CLK ST_CAL MIN 4 tCLK END_CAL ~17,400 CLK CYCLES
Figure 8. Timing for Start and End of Calibration
OE tAC D0-D15 DOR Z Z tREL
Z = HIGH IMPEDANCE (THREE-STATED)
Figure 9. Timing for Bus Access and Bus Relinquish-- Controlled by Output Enable (OE)
Two's Complement Output
The MAX1200 outputs data in two's complement format. Table 1 shows how to convert the various fullscale inputs into their two's complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR(MAX) = (6.02 * N + 1.76)dB In reality, there are other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental, the first nine harmonics, and the DC offset.
N AIN tCH
N+1 N+2 tCL N+4 N+3
N+5
CLK SAMPLE CLOCK tS DAV D0-D15 tOD N-3 N-2 N-1 N N+1
Figure 7. Main Timing Diagram
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
Table 1. Two's Complement Output Codes
SCALE +FSR - 1LSB +3/4FSR +1/2FSR +1/4FSR +0 -0 -1/4FSR -1/2FSR -3/4FSR -FSR +1LSB -FSR OFFSET BINARY 1111 .... 1111 1110 .... 0000 1100 .... 0000 1010 .... 0000 1000 .... 0000 ---- .... ---- 0110 .... 0000 0100 .... 0000 0010 .... 0000 0000 .... 0001 0000 .... 0000 ONE'S COMPLEMENT 0111 .... 1111 0110 .... 0000 0100 .... 0000 0010 .... 0000 0000 .... 0000 ---- .... ---- 1110 .... 0000 1100 .... 0000 1010 .... 0000 1000 .... 0001 1000 .... 0000 TWO'S COMPLEMENT 0111 .... 1111 0110 .... 0000 0100 .... 0000 0010 .... 0000 0000 .... 0000 1111 .... 1111 1101 .... 1111 1011 .... 1111 1001 .... 1111 1000 .... 0000 ---- .... ----
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency's RMS amplitude to all other ADC output signals: SINAD (dB) = 20log [SignalRMS / (Noise + Distortion)RMS]
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the performance of the MAX1200. At 16-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections; this adversely affects the SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX1200. Therefore, grounding and power-supply decoupling guidelines should be closely followed. First, a multilayer printed circuit board (PCB) with separate ground and power-supply planes is recommended. Run high-speed signal traces directly above the ground plane. Since the MAX1200 has separate analog and digital ground buses (AGND and DGND respectively), the PCB should also have separate analog and digital ground sections connected at only one point (star ground). Digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. Digital signals should be kept far away from the sensitive analog inputs, reference input senses, common-mode input, and clock input.
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, the effective number of bits can be calculated as follows: ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first nine harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V + V + V + + V 2 3 4 9 THD = 20log V1 where V1 is the fundamental amplitude, and V2 through V9 are the amplitudes of the 2nd through 9th-order harmonics.
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
The MAX1200 has three power-supply inputs: analog V DD (AV DD ), digital V DD (DV DD ), and drive V DD (DRVDD). Each AVDD input should be decoupled with parallel ceramic chip capacitors of values 0.1F and 0.001F, with these capacitors as close to the pin as possible and with the shortest possible connection to the ground plane. The DVDD pins should also have separate 0.1F capacitors again adjacent to their respective pins, as should the DRVDD pin. Minimize the digital load capacitance. However, if the total load capacitance on each digital output exceeds 20pF, the DRVDD decoupling capacitor should be increased or, preferably, digital buffers should be added. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PCB. Ferrite beads with additional decoupling capacitors forming a pi network may improve performance. The analog power-supply input (AV DD ) for the MAX1200 is typically +5V while the digital supplies can vary from +3V to +5V. Usually, DVDD and DRVDD pins are connected to the same power supply. Note that the DVDD supply voltage must be greater than or equal to the DRVDD voltage. For example, a digital +3.3V supply could be connected to DRVDD while a cleaner +5V supply is connected to DV DD , resulting in slightly improved performance. Alternatively, the +3.3V supply could be connected to both DRV DD and DV DD . However, the +3.3V supply must not be connected to DVDD while the +5V supply is connected to DRVDD (Table 2).
Table 2. Power-Supply Voltage Combinations
AVDD (V) +5 +5 +5 +5 DVDD (V) +5 +5 +3.3 +3.3 DRVDD (V) +5 +3.3 +3.3 +5 ALLOWED/ NOT ALLOWED Allowed Allowed Allowed Not Allowed
Chip Information
TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED TO AGND
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200
Package Information
MQFP44.EPS
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+5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC
NOTES
MAX1200
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+5V Single-Supply, 1Msps, 16-Bit Self Calibrating ADC MAX1200
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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